The present invention relates to a method of calculating the resistance of a wiring path of a semiconductor circuit and a CAD (computer aided design) system for designing a semiconductor circuit, having a function of calculating the resistance of each wiring path of the semiconductor circuit. In particular, the present invention relates to a method of accurately calculating the resistance of a wiring path that involves wires formed on different wiring layers and a contact hole for connecting the wires to each other.
CAD systems are widely used to design semiconductor circuits. For example, a logic circuit CAD system has a function design block for designing functions of a semiconductor circuit, an automatic logic design block for automatically designing logic circuits according to the designed functions, an automatic layout block for automatically laying out logic elements and signal and power source lines connected to the logic elements, and a test block for simulating the designed circuit. These blocks are systematically operated. The designed circuit is simulated to see whether or not the resistance of each wiring path has a required value. For this purpose, the CAD system has a block for calculating the resistance of each wiring path. The CAD system is constructed in a computer, and the functions thereof are realized by software.
FIG. 6 is a diagram illustrating wiring paths whose resistances are going to be calculated. Metal wires 111, 112, 113, and 114 are formed on an upper wiring layer, metal wires 121 and 122 are formed on a lower wiring layer, and contact holes 131 and 132 are formed to connect the wires to one another. The wires have ends A, B, C, D and E.
FIG. 7A is a section taken along a line VII--VII between ends A and B of FIG. 6, and FIG. 7B is a diagram of a model used by a prior art CAD system to calculate the resistance of a wiring path.
In FIG. 7A, the upper wires 111, 112, and 113 are orthogonal to the lower wires 121 and 122 and are connected thereto through the contact holes 131 and 132. When calculating the resistance of a contact hole, the prior art system employs the model of FIG. 7B. The prior art system considers the contact hole to have a single resistance Rh, and the wires to have resistances Rp, Rq, Rr, and Rs, respectively. The resistance of a wiring path from P to Q is Rp+Rh+Rq, and the resistance of a wiring path from P to S is Rp+Rh+Rs. Namely, the prior art considers that these wiring paths have the same resistance.
FIG. 8 is a diagram of a model showing the resistances of the elements of FIG. 7B. The upper wires 111, 112, 113, and 114 have resistances R1ca, Rcacb, Rcb2, and Rcb5, respectively. The lower wires 121 and 122 have resistances Rca3 and Rcb4, respectively. The contact holes 131 and 132 have resistances Rh1 and Rh2, respectively. These elements are connected to one another as shown in FIG. 8. The resistance of each wiring path is calculated as follows:
______________________________________ A to B = R1ca + Rh1 + Rcacb + Rh2 + Rcb2 A to C = R1ca + Rh1 + Rca3 A to D = R1ca + Rh1 + Rcacb + Rh2 + Rcb4 A to E = R1ca + Rh1 + Rcacb + Rh2 + Rcb5 ______________________________________
The resistances of the other wiring paths are calculated similarly.
The prior art resistance calculation illustrated by FIGS. 7A, 7B and 8 considers a contact hole to have a fixed resistance when calculating the resistance of a wiring path that involves the contact hole and wires connected thereto, without regard to whether the wires are on an upper wiring layer, a lower wiring layer, or both. A contact hole consists of an upper contact layer, a lower contact layer, and an intermediate contact layer between the upper and lower contact layers. When wires which form a wiring path with the contact hole, are both on the upper wiring layer, the actual resistance of the contact hole in the wiring path is close to the resistance of the upper contact layer. When the wires are both on the lower wiring layer, the actual resistance of the contact hole in the wiring path is close to the resistance of the lower contact layer. When the wires of the wiring path are on the upper and lower wiring layers, respectively, the actual resistance of the contact hole in the wiring path is close to the total resistance of the contact hole. As a result, the prior art resistance calculation method will be correct only when wires which form a wiring path with the contact hole, are on the upper and lower wiring layers, respectively. If the wires are both on the upper layer or the lower layer, the prior art resistance calculation method will cause a large error in calculating the resistance of the wiring path. Usually, the upper, intermediate, and lower contact layers of a contact hole have different resistances. If the difference between them is very large, the prior art resistance calculation method will cause a large error in calculating the resistance of a wiring path. This error increases as the number of contact holes involved in a wiring path increases.
There is a need for a CAD system which designs a semiconductor circuit that operates substantially as simulated, to eliminate the production of prototypes. To meet this requirement, it is necessary to improve the accuracy of simulations as well as the accuracy of wiring path resistance calculation.